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Nilesh K Rajbharti

from Phoenix, AZ
Age ~47

Nilesh Rajbharti Phones & Addresses

  • Phoenix, AZ
  • 10837 Royal Palm Rd, Peoria, AZ 85345
  • Goodyear, AZ
  • 12628 Ocotillo Rd, Glendale, AZ 85307
  • San Jose, CA
  • Maricopa, AZ
  • 10837 W Royal Palm Rd, Peoria, AZ 85345

Work

Company: Atmel corporation Jun 2010 Position: Director of applications engineering

Education

School / High School: University of Phoenix- Phoenix, AZ Nov 2005 Specialities: MBA

Skills

Firmware • Microcontroller • Management • C • Assembly • Python • JavaScript • Business Plan • Promotion • Product Launch

Industries

Semiconductors

Resumes

Resumes

Nilesh Rajbharti Photo 1

Nilesh Rajbharti

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Location:
Phoenix, Arizona Area
Industry:
Semiconductors
Skills:
Engineering Management
Microcontrollers
Embedded Software
Semiconductors
Embedded Systems
Software Engineering
Hardware Architecture
Device Drivers
Electrical Engineering
Firmware
C
Semiconductor Industry
Analog
Business Development
Electronics
Debugging
Marketing
Software Development
Nilesh Rajbharti Photo 2

Nilesh Rajbharti Phoenix, AZ

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Work:
Atmel Corporation

Jun 2010 to 2000
Director of Applications Engineering

Renesas Technology America, Inc
San Jose, CA
Aug 2008 to Jun 2010
Product/Segment Marketing Manager

Microchip Technology, Inc

Sep 2004 to Aug 2008
Applications Engineering Manager

Microchip Technology, Inc

May 2000 to Sep 2004
Technical Lead/Manager

Education:
University of Phoenix
Phoenix, AZ
Nov 2005
MBA

Gujarat University
Gujarat, IN
Sep 1993
BSEE in management

Arizona State University
Tempe, AZ
Computer Science

Skills:
Firmware, Microcontroller, Management, C, Assembly, Python, JavaScript, Business Plan, Promotion, Product Launch

Publications

Us Patents

Direct Memory Access Controller With Flow Control

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US Patent:
7721018, May 18, 2010
Filed:
Aug 24, 2006
Appl. No.:
11/466915
Inventors:
Nilesh Rajbharti - Glendale AZ,
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
G06F 13/28
G06F 3/00
US Classification:
710 22, 710 23, 710 26, 710 28, 710 36
Abstract:
A direct memory access controller has a data register for transferring data from a source to a destination address. A pattern register is provided and a data comparator is coupled with the data register and the pattern register for comparing the content of the data register with the content of the pattern register. A control unit coupled with the comparator controls the data flow and stops a data transfer if the comparator detects a match of the data register and the pattern register.

Direct Memory Access Controller With Error Check

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US Patent:
2008014, Jun 19, 2008
Filed:
Oct 30, 2007
Appl. No.:
11/928168
Inventors:
Gregg D. Lahti - Gilbert AZ,
Joseph W. Triece - Phoenix AZ,
Rodney J. Pesavento - Chandler AZ,
Nilesh Rajbharti - Glendale AZ,
Steven Dawson - Chandler AZ,
International Classification:
G06F 13/28
US Classification:
710 23
Abstract:
A direct memory access (DMA) controller may comprise a DMA bus, a memory coupled to the DMA bus, a DMA engine coupled with the DMA bus, a cyclic redundancy check (CRC) module coupled with the DMA engine, and a bus interface coupled to the DMA engine and the CRC module.

Method For Handling Of Wafers With Minimal Contact

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US Patent:
6318957, Nov 20, 2001
Filed:
Feb 24, 1999
Appl. No.:
9/256743
Inventors:
Paul R. Carr - Gilbert AZ
Paul T. Jacobson - Phoenix AZ
James F. Kusbel - Fountain Hills AZ
James S. Roundy - Gilbert AZ
Ravinder K. Aggarwal - Gilbert AZ
Ivo Raaijmakers - Phoenix AZ
Rod Lenz - Tempe AZ
Nilesh Rajbharti - Peoria AZ
Assignee:
ASM America, Inc. - Phoenix AR
International Classification:
B65G 4907
B65G 1133
US Classification:
414810
Abstract:
The invention is a carrier comprising three support elements connected by an underlying frame. The periphery of a wafer rests upon the support elements. The invention also comprises a wafer handler with a plurality of arms. Spacers space the carrier above a base plate associated with a station in a wafer handling area. An arm slides beneath the frame and between the spacers, but the handler does not contact the wafer. A method of using the handler and carrier is provided where the handler lifts and rotates the carrier with the wafer through various stations in a wafer handling area. A control device reduces the handler speed only at critical points of the processing cycle. The handler is capable of moving a plurality of carriers and wafers simultaneously.
Nilesh K Rajbharti from Phoenix, AZ, age ~47 Get Report